Memories in which data is permanently written are required for many electronic systems. Such memories are referred to as, among other things, read-only memories, read memories or read-only memory.
Compact disks are employed as read memories for very large data sets. These are plastic disks with a coating of aluminum in which two types of dot-like depressions are arranged. The information is digitally stored in the arrangement of these depressions. For reading data stored on a compact disk, the disk is mechanically rotated in a read device and the dot-like depressions are scanned Five gigabits of information can be stored on a compact disk.
A read device comprises moving parts that are subject to mechanical wear, that require a comparatively large volume, and that only allow a slow data access. Further, the read device is sensitive to jolts and can therefore be applied in only limited fashion in mobile systems.
Read-only memories on a semiconductor basis, by contrast, allow a random access to the stored information. Over and above this, they can be utilized for mobile systems since a mechanical drive is not required for reading the information. MOS transistors are usually employed in these read-only memories. Whether a current flows through the transistor or not is evaluated in the read process. Stored information is correspondingly allocated. Technically, the storing of the information is usually effected in that the MOS transistors exhibit different cut-off voltages due to different implantations in the channel region.
A storage density that can be achieved in read-only memories on a semiconductor basis is dependent on an area requirement per memory cell.
German Patent Application No. DE 195 10 042 has proposed a read-only memory cell arrangement that comprises MOS transistors arranged in lines. The MOS transistors are series-connected in each line. In order to increase the storage density, neighboring lines are respectively arranged at the floor of strip-shaped longitudinal trenches and at the surface of a substrate between neighboring, strip-shaped longitudinal trenches. Source/drain regions connected to one another are fashioned as an interconnect, doped region. The MOS transistors are read by a line-by-line arive similar to a xe2x80x9cNANDxe2x80x9d architecture.
The programming of the described memory cell arrangements ensues during manufacture. Memories into which data can be written by electrical programming, however, are required for many applications. The storing of information in electrically programmable memory cell arrangements is usually effected in that a floating gate that can be charged with an electrical charge or a in that double layer of SiO2 and Si3N4 as gate dielectric at whose boundary surface electrical charge carriers can be held fast at traps is provided between the gate and the channel region of the MOS transistors. The cut-off voltage of the MOS transistor is dependent on the charge located on the floating gate or, the traps. This property is utilized for electrical programming (see, for example, S. M. Sze, Semiconductor Devices, John Wiley, pages 486 through 490).
It is an object of the present to provide a memory cell arrangement that is electrically programmable and that is suitable for storing large data sets. It is further object of the invention to provide a method for the manufacture thereof. These objectives are achieved in accordance with the invention in a memory cell arrangement and a method for the manufacture thereof.
The memory cell arrangement comprises a number of memory cell lines in a semiconductor substrate. Neighboring memory cell lines are insulated from one another.
The memory cell lines respectively comprise a first doped region and a second doped region. A gate dielectric and a number of gate electrodes arranged next to one another are arranged at a principal surface of the semiconductor substrate between the first doped region and the second doped region. The spacing between neighboring gate electrodes is thereby less than the dimensions of the gate electrodes parallel to the connecting line between the first doped region and the second doped region. The gate dielectric contains a material having charge carrier traps.
Traps have the properties of trapping charge carriers, specifically electrons. For electrical programming, the gate electrodes are wired such that charge carriers corresponding to the information to be stored proceed into the gate dielectric under the gate electrode and are held fast by the traps. Since the charge carriers are trapped in the traps, the information is durably stored. The programmed memory cell arrangement therefore represents a read-only memory cell arrangement. The programming can ensue both by Fowler-Nordheim-tunneling as well by hot electron injection. Charge carriers can be removed from the traps by reversing the polarities in the Fowler-Nordheim tunneling, so that the programming of the memory cell arrangement can be modified.
The invention is based on the following considerations: when driving a line in which series-connected MOS transistors are arranged in the sense of an xe2x80x9cNANDxe2x80x9d architecture, the gate electrodes of the MOS transistors are wired such that all MOS transistors except the selected MOS transistors conduct, regardless of the cut-off voltage of the individual transistor that is not selected. This is effected in that a voltage is applied to the gate electrode that is higher than the highest cut-off voltage that occurs. The gate electrode of the selected MOS transistor, by contrast, is charged with a voltage that lies between the cut-off voltages of the MOS transistors. An evaluation is made to determine whether a current flows across the series-connected MOS transistors or not. When a current flows, then the information corresponding to the lower cut-off voltage is stored in the selected MOS transistor. When no current flows, then the information is stored corresponding to the higher cut-off voltage.
The invention makes use of the principle that most source/drain regions of these MOS transistors act merely as a conductive connection between neighboring, conductive channels upon read-out. A doped region corresponding to a source/drain region is therefore arranged only at the start and at the end of each memory cell line in the inventive memory cell arrangement, gate electrodes arranged tightly side-by-side between these doped regions effecting a space charge zone up to the channel region of the selected gate electrode on the basis of a corresponding wiring. In this way, the space requirement for source/drain regions arranged between two neighboring gate electrodes is eliminated in the memory cell lines. The stray field between neighboring, driven gate electrodes thereby causes the region under the interspaces between neighboring gate electrodes to be made conductive. The spacing between neighboring gate electrodes is preferably amounts to 10 through 100 nm.
In applications wherein the stray field between neighboring, driven gate electrodes is not adequate in order to make the region under the interspace between the neighboring gate electrodes conductive, it lies within the scope of the invention to modulate the dopant distribution at the surface in this region with an opposite doping. A dopant concentration in the region of 1017 cmxe2x88x923 is adequate for this purpose. This dopant concentration is clearly lower than in the first doped region and the second doped region that, like source/drain regions, exhibit a dopant concentration in the range from 1020 through 1021 cmxe2x88x923. The opposite doping merely serves for the modulation of neighboring space charge zones. It is not comparable to standard source/drain regions.
For storing data in digital form, different charge quantities are introduced into the gate dielectric under the gate electrodes, so that two different cut-off voltages arise in the arrangement. When the memory cell arrangement is to be utilized for polyvalent logic, then the gate dielectric is charged with different charge quantities in the programming by corresponding voltage and time conditions suck that more than two different cut-off voltages are realized dependent on the information stored.
According to one embodiment of the invention, the gate dielectric is fashioned as a dielectric multiple layer wherein at least one layer is provided that, compared to at least one further layer in the dielectric multiple layer, exhibits an increased charge carrier capture cross-section. The traps are localized at the boundary surface between the two layers. The dielectric multiple layer preferably comprises a SiO2 layer, and aSi3N4 and a SiO2 layer (what is referred to as ONO). Alternatively, the dielectric multiple layer can be composed of other materials, whereby the layer having the increased charge carrier capture cross-section is composed, for example, of Si3N4, Ta2O5, Al2O3 or of TiO2 and the neighboring layer is composed of SiO2, Si3N4, or Al2O3. Further, the dielectric multiple layer can comprise more than three layer or fewer than three layers.
Alternatively, the gate dielectric can comprise a dielectric layer of such as , SiO2 into which foreign atoms, for example W, Pt, Cr, Ni, Pd or Ir, are embedded. The embedded foreign atoms can be introduced by implantation, by addition in an oxidation or by diffusion. The embedded foreign atoms form the traps in this case.
Neighboring memory cell lines can be insulated by insulating the trenches arranged therebetween or the pn-junctions arranged therebetween or can be insulated in that parallel, strip-shaped trenches are provided in the principal surface of the semiconductor substrate, and the memory cell lines are respectively arranged in alternation at the floor of the trenches and at the principal surface between neighboring trenches.
The employment of insulating trenches or insulating pn-junctions between neighboring memory cell lines has the advantage that the memory cell arrangement is planar, which reduces the number of required process steps and the process complexity.
The insulation of the neighboring memory cell lines by arrangement at the floor and between neighboring trenches, by contrast, enables a further enhancement and of the storage density, since the insulation between neighboring memory cell lines is realized by trench wall.
The memory cell lines act as bit lines in the memory cell arrangement. The gate electrodes are connected to word lines proceeding transversely relative to the memory cell lines. Preferably, the gate electrodes are fashioned strip-shaped of conductive material, so that the strip-shaped gate electrodes form the word lines.
When the gate electrodes are formed in a tight grid, for example with a spacing between neighboring gate electrodes having a minimum structural size F, then it lies within the scope of the invention to provide the gate electrodes with expanded portions at which contacts are applied for easier contacting of the gate electrodes. The expanded portions of neighboring gate electrodes are thereby arranged offset relative to one another. The gate electrodes are preferably formed as strip-shaped structures, wherein steps are provided in the long sides of the gate electrodes in the region of the expanded portions. As a result of an offset arrangement of these steps along neighboring gate electrodes, the additional space requirement for the expanded portions is limited to the width of an expanded portion.
For driving the bit lines, it lies within the scope of the invention to merge a number of neighboring bit lines in a node and to provide a selection switch or a decoder between the node and the doped region that ends the memory cell line. To that end, at least one MOS transistor is respectively formed between the node and the doped region, this MOS transistor being driveable via a selection electrode. The selection electrode is thereby realized as a selection line that proceeds transversely relative to the bit lines. Such a doping is produced under the corresponding selection line by a channel implantation at the points of intersection of the selection line with the bit line, which should exhibit no selection transistor at the point of intersection, namely such that the parasitic MOS transistor formed under the selection line exhibits such a low cut-off voltage that it conducts regardless of whether a voltage is applied to the selection line or not.
When a selection switch is formed between the node and the doped regions, then the number of selection lines formed is the same as the number of bit lines that are merged. The selection transistors are generated along the diagonals of the intersecting points between the selection lines and the bit lines.
When a decoder is formed between the node and the doped regions, then, when 2n bit lines are merged in the node, 2n selection lines are formed. Two neighboring selection lines are thereby complementary relative to one another with respect to the arrangement of the selection transistors. MOS transistors are arranged next to one another or, no MOS transistors are arranged in every nth selection lying pair at respectively 2nxe2x88x921 intersecting points of the selection lines with the bit lines.
For manufacturing the memory cell arrangement, a number of memory cell lines that are insulated from one another are generated in a semiconductor substrate, preferably a monocrystalline silicon wafer or/a silicon layer of a SOI substrate. A first doped region and a second doped region are formed for each memory cell line in the semiconductor substrate.
A dielectric layer that contains a material having charge carrier traps is formed. A first electrode layer is generated thereon and structured for forming first gate electrodes. Spaces are formed at the side walls of the first gate electrodes. A second dielectric layer is formed that contains a material having charge carrier traps. For forming second gate electrodes, a second electrode layer having essentially conformal edge coverage is generated and structured. The first gate electrodes and the second gate electrodes are respectively arranged next to one another, wherein the spacing between neighboring gate electrodes is smaller than the dimensions of the gate electrodes parallel to the connecting line between the first doped region and the second doped region.
It lies within the scope of the invention to selectively remove the spacers between the first gate electrodes and the second electrodes relative to the first gate electrodes and the second gate electrodes and to undertake an opposite self-aligned doping, thereby modulating the doping of the semiconductor substrate in the region between the first gate electrodes and the second gate electrodes. The opposite doping ensues with a dopant concentration in a range between below 5xc3x971017 cmxe2x88x923. Preferably, the opposite doping is set to a somewhat higher value, for example to two to three times the dopant concentration that is employed as channel doping of a MOS transistor in the technology employed.
For insulation between neighboring memory cell lines, it lies within the scope of the invention to form strip-shaped insulation trenches between the neighboring memory cell lines with the assistance of a shallow trench isolation (STI) technology. When the gate electrodes are formed with a spacing corresponding to a minimum structural size F and when the memory cell lines as well as the isolation trenches respectively exhibit a width that is Also F, then an area requirement per memory cell of 2F2 derives in this case, leaving the surface requirement of the first doped regions and of the second doped regions out of consideration.
It lies within the scope of the invention to insulate neighboring memory cell lines in that they are respectively formed in alternation at the floor of stripe-shaped, essentially parallel trenches and between the trenches at the principal surface of the semiconductor substrate. In this case, the sidewall of the trenches acts as insulation between the neighboring memory cell lines. When, in this case, the gate electrodes are formed with a spacing between their centers having a minimum structural size F and the trenches are Also formed with a spacing of their centers having a structural size F, then, leaving the space requirement for the first doped regions of the second doped regions out of consideration, a space requirement per memory cell of 1F2 derives.